1. Field of the Invention
The present invention relates generally to methods for forming gate dielectric layers within semiconductor integrated circuit microelectronic fabrications. More particularly, the present invention relates to methods for forming multiple gate dielectric layers with multiple thicknesses within semiconductor integrated circuit microelectronic fabrications.
2. Description of the Related Art
Semiconductor integrated circuit microelectronic fabrications are formed from semiconductor substrates over which are formed patterned conductor layers which are separated by dielectric layers.
As semiconductor integrated circuit microelectronic fabrication integration levels have increased and semiconductor integrated circuit microelectronic fabrication functionality levels have increased, it has become increasingly common in the art of semiconductor integrated circuit microelectronic fabrication to form within semiconductor integrated circuit microelectronic fabrications pluralities of semiconductor devices which are formed with corresponding pluralities of gate dielectric layers having corresponding pluralities of gate dielectric layer thicknesses. Within the context of the present invention, gate dielectric layers are intended as dielectric layers which are formed directly upon semiconductor substrates, whether or not they are employed within field effect transistor (FET) devices, although gate dielectric layers are most typically employed within field effect transistor (FET) devices within semiconductor integrated circuit microelectronic fabrications. Similarly, although gate dielectric layers within semiconductor integrated circuit microelectronic fabrications are most commonly formed employing thermal oxidation methods, gate dielectric layers within semiconductor integrated circuit microelectronic fabrications may also be formed employing various combinations of thermal oxidation methods, deposition methods and nitridation methods.
It has become increasingly common in the art of semiconductor integrated circuit microelectronic fabrication to form within semiconductor integrated circuit microelectronic fabrications pluralities of semiconductor devices which are formed with corresponding pluralities of gate dielectric layers having corresponding pluralities of gate dielectric layer thicknesses insofar as the functional requirements and operational requirements of the pluralities of semiconductor devices formed within the semiconductor integrated circuit microelectronic fabrications often demand the plurality of gate dielectric layers having the plurality of gate dielectric layer thicknesses. For example and without limitation, within embedded semiconductor integrated circuit microelectronic fabrications (i.e., semiconductor integrated circuit microelectronic fabrications which perform both a logic function and a memory function), it is common to employ comparatively thin gate dielectric layers within field effect transistor (FET) devices which perform the logic function, such as to enhance operating speed of the field effect transistor (FET) devices which perform the logic function, while employing comparatively thick gate dielectric layers within field effect transistor (FET) devices which perform memory functions or other peripheral functions, wherein the field effect transistor (FET) devices which perform the memory function or other peripheral function may be subject to comparatively higher operating voltages.
While it is thus desirable in the art of semiconductor integrated circuit microelectronic fabrication to provide pluralities of semiconductor devices having corresponding pluralities of gate dielectric layers in turn having corresponding pluralities of gate dielectric layers thicknesses, and often unavoidable in the art of semiconductor integrated circuit microelectronic fabrication to provide pluralities of semiconductor devices having corresponding pluralities of gate dielectric layers in turn having corresponding pluralities of gate dielectric layer thicknesses, forming within semiconductor integrated circuit microelectronic fabrications such semiconductor devices having corresponding pluralities of gate dielectric layers in turn having corresponding pluralities of gate dielectric layer thicknesses is not entirely without problems in the art of semiconductor integrated circuit microelectronic fabrication.
In that regard, it is often difficult to form within semiconductor integrated circuit microelectronic fabrications pluralities of semiconductor devices having corresponding pluralities of gate dielectric layers in turn having corresponding pluralities of gate dielectric layer thicknesses with enhanced manufacturability and reliability of the semiconductor integrated circuit microelectronic fabrications.
It is thus desirable in the art of semiconductor integrated circuit microelectronic fabrication to form within semiconductor integrated circuit microelectronic fabrications pluralities of semiconductor devices having corresponding pluralities of gate dielectric layers in turn having corresponding pluralities of gate dielectric layers thicknesses, with enhanced manufacturability and reliability of the semiconductor integrated circuit microelectronic fabrications.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed in the art of semiconductor integrated circuit microelectronic fabrication for forming, with corresponding pluralities of gate dielectric layers having corresponding pluralities of gate dielectric layer thicknesses, pluralities of semiconductor devices within semiconductor integrated circuit microelectronic fabrications.
Included among the methods, but not limiting among the methods, are methods disclosed within: (1) Barsan et al., in U.S. Pat. No. 5,672,521 (a method which employs implanting into a first region of a silicon semiconductor substrate a dose of a dopant which enhances thermal oxidation of the silicon semiconductor substrate and implanting into a second region of the silicon semiconductor substrate a dose of a nitrogen dopant which inhibits thermal oxidation of the silicon semiconductor substrate, such that upon thermal oxidation of the silicon semiconductor substrate including the first region, the second region and an unimplanted third region there is formed upon the silicon semiconductor substrate a gate dielectric layer having three thickness regions); (2) Chwa et al., in U.S. Pat. No. 6,147,008 (a method which employs implanting through a gate dielectric layer formed upon a silicon semiconductor substrate a dose of a nitrogen implanting ion which inhibits thermal oxidation of the silicon semiconductor substrate and then patterning the gate dielectric layer to form a patterned gate dielectric layer which leaves exposed implanted and unimplanted portions of the silicon semiconductor substrate, prior to thermally oxidizing the silicon semiconductor substrate to reform a gate dielectric layer having three thickness regions); (3) Song, in U.S. Pat. No. 6,191,049 (an additional ion implanting method which employs nitrogen implanting ions and fluorine implanting ions to assist in providing a semiconductor substrate which upon thermal oxidation may have formed thereupon a gate dielectric layer with three thickness regions); (4) Balasubramanian et al., in U.S. Pat. No. 6,235,591 (a sequential thermal annealing method for forming differential gate oxide layer thicknesses within semiconductor integrated circuit microelectronic fabrications with enhanced reliability by employing a bilayer sacrificial mask layer formed of other than a photoresist material); and (5) Huang, in U.S. Pat. No. 6,265,267 (an integrated method for fabricating a flash memory semiconductor integrated circuit microelectronic fabrication having multiple gate dielectric layer thicknesses while employing a polysilicon layer as an oxidizable and sacrificial layer with respect to an intergate dielectric layer within a split gate field effect transistor (FET) device within the flash memory semiconductor integrated circuit microelectronic fabrication).
Desirable in the art of semiconductor integrated circuit microelectronic fabrication are additional methods for forming within semiconductor integrated circuit microelectronic fabrications pluralities of semiconductor devices having corresponding pluralities of gate dielectric layers in turn having corresponding pluralities of gate dielectric layer thicknesses, with enhanced manufacturability and reliability of the semiconductor integrated circuit microelectronic fabrications.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a method for forming within a semiconductor integrated circuit microelectronic fabrication a plurality of semiconductor devices having a corresponding plurality of gate dielectric layers having a corresponding plurality of gate dielectric layer thicknesses.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the semiconductor integrated circuit microelectronic fabrication is formed with enhanced manufacturability.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a semiconductor integrated circuit microelectronic fabrication and a method for fabricating the semiconductor integrated circuit microelectronic fabrication.
In accord with the present invention, and within the context of a somewhat narrower embodiment of the present invention, the semiconductor integrated circuit microelectronic fabrication comprises: (1) a semiconductor substrate; (2) at least a first gate dielectric layer, a second gate dielectric layer and a third gate dielectric layer formed laterally adjacent upon the semiconductor substrate; and (3) at least a first polysilicon containing gate electrode formed upon the first gate dielectric layer, a second polysilicon containing gate electrode formed upon the second gate dielectric layer and a third polysilicon containing gate electrode formed upon the third gate dielectric layer. Further in accord with the present invention: (1) the first gate dielectric layer is formed to a first thickness, and the second gate dielectric layer and the third gate dielectric layer are both formed to a second thickness different than the first thickness; and (2) the second polysilicon containing gate electrode has a first dopant distribution profile different in comparison with a second dopant distribution profile of the third polysilicon containing gate electrode such as to provide an apparent difference in thickness of the second gate dielectric layer with respect to the second polysilicon containing gate electrode and the third gate dielectric layer with respect to the third polysilicon containing gate electrode when the first polysilicon containing gate electrode, the second polysilicon containing gate electrode and the third polysilicon containing gate electrode are employed within a series of field effect devices within the semiconductor integrated circuit microelectronic fabrication.
Within the context of a broader embodiment of the present invention, the present invention encompasses a semiconductor integrated circuit microelectronic fabrication predicated upon dopant distribution profile differences within multiple polysilicon containing gate electrodes to effect differences in apparent thicknesses of single actual thickness gate dielectric layers upon which they are formed when the multiple polysilicon containing gate electrodes are employed within multiple field effect devices within the semiconductor integrated circuit microelectronic fabrication. Within the broader embodiment of the present invention, physical thickness differences of gate dielectric layers need not necessarily be present.
The semiconductor integrated circuit microelectronic fabrications in accord with the present invention contemplate corresponding methods for fabricating the semiconductor integrated circuit microelectronic fabrications in accord with the present invention.
There is provided by the present invention a method for forming within a semiconductor integrated circuit microelectronic fabrication a plurality of semiconductor devices having a corresponding plurality of gate dielectric layers having a corresponding plurality of gate dielectric layer thicknesses, wherein the semiconductor integrated circuit microelectronic fabrication is formed with enhanced manufacturability and reliability.
The present invention realizes the foregoing object by fabricating a semiconductor integrated circuit microelectronic fabrication such as to provide at least a pair of different dopant distribution profiles within a pair of polysilicon containing gate electrodes formed upon a pair of gate dielectric layers of a single thickness such as to provide different effective thicknesses of the pair of gate dielectric layers when the pair of gate electrodes is employed within a pair of field effect devices within the semiconductor integrated circuit microelectronic fabrication. The present invention may further employ additional gate electrodes formed upon additional gate dielectric layers of different thicknesses within the semiconductor integrated circuit microelectronic fabrication.
The method of the present invention is readily commercially implemented.
The present invention employs methods and materials as are otherwise generally conventional in the art of semiconductor integrated circuit microelectronic fabrication, but employed within the context of specific materials limitations and specific process limitations to provide the present invention. Since it is thus at least in part specific materials limitations and specific process limitations which provide at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.